DCDC_EN_CLAMP_LO=Val_0, DCDC_EN_CLAMP_HI=Val_0, DCDC_VOUT_SEL=Val_0b00
DC/DC Control Register 1
| DCDC_EN_CLAMP_HI | Enable Vcomp clamp for voltages over 1.3 V: 0 (Val_0): Disable clamp 1 (Val_1): Enable clamp |
| DCDC_EN_CLAMP_LO | Enable Vcomp clamp for voltages less than 400 mV: 0 (Val_0): Disable clamp 1 (Val_1): Enable clamp |
| FORCE_LS_ON | Force low-side Power FET to be on (NMOS Power FET), PWM signal will be kept low. |
| DCDC_VOUT_SEL | Select DC-DC regulation reference voltage: 0 (Val_0b00): Vref = 0.800 V 1 (Val_0b01): Vref = 0.800 V 2 (Val_0b10): Vref = 0.825 V 3 (Val_0b11): Vref = 0.850 V |
| DCDC_TRIM_VOUT | Trim DC-DC regulation reference voltage: Min is 0000: -4% Max is 1111: +3.5% Step: 0.5% |
| DCDC_OSC2M_IBIAS | Trim DC-DC 2-MHz internal oscillator: Min is 0000: 1.5 MHz Max is 1111: 3.75 MHz Step = ~0.15 MHz |
| DCDC_CTRL_FET | Selects the drive strength of DC-DC NFET power transistor |
| DCDC_EN_XTAL_CLK | Switch DC-DC PWM clock from internal 2-MHz oscillator to 2-MHz crystal oscillator when = 1. |
| EN_DRV_DLY_CONT | Trim EN_DRV signal delay: Min is 0000 = 0 clock cycle delay Max is 1111 = 15 clock cycle delay Clock is DC-DC clock divided by 8 (~250 kHz for nominal settings) |
| EN_SS_DLY_CONT | Trim EN_SS signal delay: Min is 0000: 0 clock cycle delay Max is 1111: 15 clock cycle delay Clock is DC-DC clock divided by 8 (~250 kHz for nominal settings) |
| DIS_MIN_TON | If = 1, disables the minimum ‘ON time’ of HS FET (PMOS), and minimum ‘ON time’ of LS FET (NMOS). |
| RAMP_CONT | Select VDD_MAIN feed forward ramp current. For VDD_MAIN = 3.6 V: Min: 000 = 6 uA Max: 111 = 13 uA Step: 1 uA This current is proportional to VDD_MAIN voltage. |
| TRIM_CRAMP | Feed forward ramp capacitor adjust |